1. Field of Application
The present invention relates to a fault detection apparatus for detecting failure of an A/D (analog-to-digital) converter, and in particular to a fault detection apparatus for an A/D converter which operates from an externally supplied clock signal, whereby the fault detection apparatus can detect failure caused by loss of that clock signal.
2. Description of Related Art
A type of A/D converter is known, for example as described in Japanese Patent Publication No. 2006-304365 (referred to in the following as reference document 1), having three or more channels with respective input terminals, for inputting respective analog voltage signals, with the analog voltage signals being converted to digital values. With the apparatus of reference document 1, failure of the A/D converter is detected as follows. At least two analog voltages are predetermined, and the respectively corresponding digital values that result from A/D conversion of these analog voltages (i.e., when the A/D converter is operating normally) are also predetermined. A/D conversion is applied to the two analog voltages and the relationship between the digital values resulting from that conversion is compared with a predetermined relationship. If the detected relationship does not correspond to the predetermined relationship, then it can be determined that there is failure of the A/D converter.
In the case of an A/D converter which performs conversion in synchronism with an externally supplied clock signal (referred to in the following simply as an external clock signal), if the signal lead through which the external clock signal is supplied should become open-circuited, the A/D conversion will cease to be synchronized with the external clock signal. Hence, digital data will be outputted which have been derived through A/D conversions performed at random timings. Thus is necessary to be able to detect such an occurrence, as a failure of the A/D converter. However the apparatus of reference document 1 does not detect an A/D converter failure that results from an open-circuit of the connecting lead that supplies the external clock signal. Furthermore, the failure detection method that is used with reference document 1 is applicable only to an A/D converter having three or more signal input channels, and in particular, cannot be used in the case of an A/D converter having a single input channel.